In many applications, signals that are generated at a first location and transmitted to a second location need to arrive at the second location having a desired phase. It may be difficult, however, to control the phase in cases where the signal path length from the first to the second location is not well known. This may be the case, for example, when clock generators generate clock signals that are to be sent to multiple devices over different signal paths on a board. Though it may be desirable for the clock signals to arrive at the devices having the same phase, differences in delays that may be added by the different signal paths, for example, may lead to the clock signals arriving at the different devices having different phases.
Turning to FIG. 1, an example of a conventional clock distribution network 100. Network 100 generally comprises a PLL 102, compensation circuits 104-1 to 104-N (which respectively include DLLs 106-1 to 106-N and delay controllers 108-1 to 108-N), and devices under test (DUTs) 110-1 to 110-N. As can be seen, the compensation circuits 104-1 to 104-N are located near the DUTs 110-1 to 110-N, allowing for manual skew compensation. As a result, calibrating the network 100 is time consuming and difficult, and any changes to the network 100 would generally require recalibration